The present invention generally relates to the technology of CMP (chemical mechanical polishing) and more particularly to fabrication process of a semiconductor device including a polishing process conducted by CMP technology.
In the production of semiconductor devices, the technology of CMP (Chemical Mechanical Polishing) is extensively used for planarizing a substrate or removing insulation films or conductive films.
Especially, a CMP process is important in the process of forming a multilayer interconnection structure, which uses low-resistance metals such as Cu as an interconnection layer. Further, a CMP process is important not only in surface treatment of silicon wafers and magnetic disks but also in polishing optical elements such as lens.
FIGS. 1A-1E show the fabrication process of a conventional semiconductor device including a Cu damascene process.
Referring to FIG. 1A, an insulation film 21 of SiO2, SiOC, SiC, SiON, SiN, BPSG, and the like, is formed on a semiconductor substrate (not shown) so as to cover an active device such as transistor not illustrated. The insulation film 21 may be formed directly on the semiconductor substrate or on an insulation film formed on the semiconductor substrate.
Next, in the step of FIG. 1B, an interconnection trench 21G corresponding to a desired interconnection is formed in the insulation film 21 by etching. In the case of dual damascene process, a via-hole is formed in the interconnection trench 21G so as to expose the conductive layer lying under the insulation film 21.
Further, in the step of FIG. 1C, the surface of the insulation film 21 is covered with a barrier metal film 22 of tantalum (Ta), titanium (Ti) or nitride thereof (TaN, TiN) including the sidewall surface and bottom surface of the interconnection trench 21G.
Next, in the step of FIG. 1D, a Cu film 23 is formed on the barrier metal film 23 such that the Cu film 23 fills the interconnection trench 21G, wherein such formation of the Cu film 23 is implemented by a sputtering process or plating process, or combination of these.
Further, in the step of FIG. 1E, the Cu film 23 is removed from the surface of the insulation film 21 by using a CMP apparatus together with the barrier metal film 23, and an interconnection structure is obtained such that a Cu pattern 23G is buried in the interconnection trench 21G via the barrier metal film 22.